library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity FLIP_FLOP_D is
    generic(
            P: natural
    );
    port(
          clk: in std_logic;
          input: in std_logic_vector (P-1 downto 0);
          output: out std_logic_vector (P-1 downto 0)
   	);
end entity;
   	
architecture FF of FLIP_FLOP_D is    
begin
   process(clk)
   begin
       if rising_edge(clk) then
              output<=input;
       end if;
   end process;
end FF;